FIGS. 9(a) to 9(f) are sectional views illustrating process steps in a prior art method for producing an FET.
Initially, an image reversal photoresist film 2 about 0.6 .mu.m thick is deposited on a semi-insulating GaAs substrate 1 about 600 .mu.m thick including an active region (not shown) about 5000.ANG. thick (FIG. 9(a)).
Using a mask shown in FIGS. 10(a)-10(b), the photoresist film 2 is selectively exposed to light having a wavelength of 0.3.about.0.4 .mu.m (first exposure step), preferably by a conventional photolithographic technique. Then, the photoresist film 2 is subjected to a reversal baking process and a whole surface exposure (second exposure step), whereby a part of the photoresist film 2 which is not exposed to light during the first exposure step is made soluble. This soluble part is removed during development, resulting in a photoresist pattern 2a with an aperture 3 0.5.about.1 .mu.m wide (FIG. 9(b)).
The image reversal process is a technique for producing a negative image using a positive photoresist. If a positive photoresist is exposed to light using the mask shown in FIGS. 10(a)-10(b), since the absorption of the exposed portion is highest in the vicinity of the surface and gradually decreases with the thickness of the photoresist film, a trapezoid photoresist pattern remains after development. However, if the positive photoresist is reversed to a negative photoresist after the exposure step, the exposed portion remains during the development, resulting in a photoresist pattern having a trapezoid aperture as shown in FIG. 9(b).
In the step of FIG. 9(c), the substrate is wet etched with a mixture of phosphoric acid and hydrogen peroxide or a mixture of tartaric acid and hydrogen peroxide using the photoresist pattern 2a as a mask (first recess etching), forming a first gate recess 4 (FIG. 9(c)). Preferably, the first gate recess 4 has a width of 1.4 .mu.m and a depth of 3000.ANG..
Thereafter, dry etching is carried out using the photoresist pattern 2a as a mask (second recess etching), forming a second gate recess 4a in the center of the bottom surface of the first gate recess 4 (FIG. 9(d)). Preferably, the second gate recess 4a has a width of 0.6 .mu.m and a depth of 1000.ANG..
A gate metal 5a, such as Al, Ti, or Au, is deposited in the direction perpendicular to the surface of the substrate 1 (FIG. 9(e)), and the photoresist pattern 2a and the overlying portions 5a of the gate metal are removed by a lift-off technique, resulting in a gate electrode 5 in the second recess 4a (FIG. 9(f)). Preferably, the gate length is 0.5 .mu.m.
In the above-described Schottky-gate field effect transistor, i.e., metal semiconductor field effect transistor (hereinafter referred to as MESFET), the gate electrode disposed in the recess is not adversely affected by a surface depletion layer due to surface states, reducing the source resistance. In addition, the electric field concentration between the gate and the drain is relaxed, increasing the drain breakdown voltage.
An offset arrangement of the gate electrode in the recess has been well known as a technique for further improving the recessed gate structure. That is, the gate electrode is disposed in the recess toward the source electrode. In this case, since the space between the gate and the source is narrowed, the source resistance is reduced. On the other hand, since the space between the gate and the drain is widened, the drain breakdown voltage is increased.
However, the offset arrangement of the gate electrode is impossible in the process steps illustrated in FIGS. 9(a)-9(f). The reason will be described hereinafter.
FIGS. 10(a) and 10(b) illustrate a mask employed in the gate pattern transfer step in the above-described production process, in which FIG. 10(a) is a plan view of the mask and FIG. 10(b) is a sectional view taken along line B--B of FIG. 10(a). In the figures, reference numeral 6 designates a glass plate. A light shielding film 7 serving as a gate pattern transfer mask is disposed on a surface of the glass plate 6. Preferably, the light shielding film 7 is made of Cr. The light shielding film 7 includes a portion 7a corresponding to a gate finger (hereinafter referred to as gate finger portion). The width of the gate finger portion 7a is 2.5.about.5 .mu.m. Reference numerals 6a and 6b designate portions of the glass plate 6 at opposite sides of the gate finger portion 7a. In this gate pattern transfer process, the reduction ratio of the gate pattern transfer mask is 1/5.
FIG. 10(c) illustrates an on-wafer intensity profile of light transmitted through the gate pattern transfer mask shown in FIGS. 10(a)-10(b) during the exposure process. As shown in FIG. 10(c), a symmetric profile with the gate finger portion 7a as the center of symmetry is attained. FIG. 10(d) illustrates the relation between the exposure energy of the exposure apparatus and the overhang of the image reversal photoresist pattern 2a in the aperture 3. As shown in FIG. 10(d), the overhang is approximately in inverse proportion to the exposure energy in a limited range of the exposure energy. An increase in the exposure energy increases the absorption at the lower part of the photoresist film 2 and decreases the overhang of the photoresist pattern 2a. That is, sufficient exposure energy produces almost vertical side surfaces of the photoresist pattern 2a in the aperture 3.
As described above, when the photoresist pattern of the gate electrode is formed using the pattern transfer mask with the symmetric light shielding film shown in FIG. 10(a), the photoresist pattern 2a with the symmetric overhanging portions in the aperture 3 is attained. Therefore, the offset arrangement of the gate electrode in the recess is impossible.
A variety of methods for the offset arrangement of the gate electrode have been proposed. Some of them will be described hereinafter.
In Japanese Published Patent Application No. 2-25039, a photoresist pattern for a gate electrode is formed on a substrate with an active region and source and drain electrodes, and wet etching is carried out after removing a portion of the photoresist pattern on the drain electrode. Since the etching rate on the drain electrode side is increased, the width of the recess on the drain electrode side is increased. In this method, however, it is difficult to control the etching rates in the perpendicular and transverse directions during wet etching and, therefore, the recess shape after the wet etching unfavorably varies, resulting in a variation in the offset position of the gate electrode.
In Japanese Published Patent Application No. 64-86564, a photoresist film is deposited on a substrate having an active region and source and drain electrodes, and an Al film with an aperture of a prescribed width is formed on the photoresist film. Using the Al film as a mask, an energy beam is obliquely applied to the photoresist film, forming a photoresist pattern with asymmetric overhanging portions. Then, the substrate is selectively etched using the photoresist pattern as a mask, forming a gate recess having an asymmetric width with respect to the aperture of the Al film. In this method, however, the formation of the mask for the energy beam irradiation, i.e., the Al film with the aperture, complicates the production process. In addition, if a common drain structure is employed, the focusing of the exposure energy beam is difficult, resulting in a variation in the recess shape.
In Japanese Published Patent Applications Nos. 2-267945, 3-145738, and 3-293733, a mask pattern having asymmetric overhanging portions in its aperture is formed on a substrate using a plurality of materials, and the substrate is etched using the mask pattern to form a recess having an asymmetric width with respect to the aperture of the mask. In this method, however, the mask formation process is complicated and the precision in forming the overhanging portions in the aperture of the mask is poor.
In the above-described prior art methods for offset-arranging the gate electrode in the recess, the recess etching is not controlled with high precision. In addition, the offset position of the gate electrode in the recess unfavorably varies due to the increased and complicated process steps.